Design of anti-interference devices

Typical interference

There are countless sources of interference that can cause failure or failure of the device. However, the following interference is most common:

Nanosecond interference caused by the operation of mechanical contacts of switches and relays. In foreign literature, this type of interference is called EFT - Electric Fast Transients
Microsecond interference associated with the work of reactive elements in the circuits of powerful loads (charging capacitors, as well as the return of energy stored in the windings of motors, solenoids, etc.) In foreign literature, this type of interference is called surge.
Interference from electrostatic discharges, mainly interference arising from the contact of different electrical circuits by an "electrified" person. In foreign literature, this type of interference is called ESD - Electrostatic Discharge.
Interference caused by the operation of nearby radio transmitters
Interference from powerful natural or artificial sources of energy, primarily from lightning discharges.

It is advisable to divide all interference into three abstract types:

NP: Nanosecond Interference
MP: Powerful interference
RP: Radio Frequency Interference

Virtually all real interference can be represented as a combination of these three abstract. For example, EFT interference is a bundle of nanosecond interference NP, and ESD is a combination of a single NP and a single MP. Therefore, if the device is resistant to all three abstract types of interference, then with a high degree of probability it will be stable to real interference, regardless of their origin.

The issue of resistance to MP is to a large extent a matter of reliability, fire safety and electrical safety. Issues of ensuring resilience to MP and RP in this article are not considered.

Nanosecond Interference

This type of interference causes most failures. With all its diversity, nanosecond interference has some common properties:

A single NP is almost a delta function, it has an extremely wide spectrum, up to gigahertz
NP has insignificant energy, unlike MP, it usually does not "burn out" electronic devices, but causes a reversible failure
Only devices with memory, such as microprocessors, counters, etc., can fail. For purely combinational digital circuits, the concept of “failure” loses its meaning, because they automatically return to the desired state at the end of the NP. Note that analog circuits can also have a "memory" in the form of capacitances or inductances.

To better understand this type of interference, it is useful to refer to the IEC 61000-4-4 standard (GOST R 51317.4.4-99). It says that EFT interference should be simulated by triangular pulse bursts. The duration of the leading edge of each pulse is 5 ns, the pulse duration is 50 ns at the level of 50%. The internal resistance of the pulse generator is 50 ohms, the generator must be grounded.

The amplitude of NP-pulses depends on which noise immunity class the device under test should belong to, as well as where the pulses are fed during testing, see Table 1. There may be more severe tests than those indicated in the table, if required by conditions operation of the device. However, in most cases, the degrees of stiffness listed in the table are sufficient. The easiest tests apply to household appliances, the toughest to industrial and on-board devices.

Table 1. Amplitudes of NP pulses

The degree of hardness testing	Power supply, grounding		I / O signals
The degree of hardness testing	Pulse amplitude, kV	Repetition frequency, kHz	Pulse amplitude, kV	Repetition frequency, kHz
one	0.5	five	0.25	five
2	one	five	0.5	five
3	2	five	one	five
four	four	2.5	2	five

In the power line and grounding test NP test pulses are injected directly, without decoupling. Given the relatively low resistance of the signal generator, the magnitude of the pulse currents flowing in the circuits of the earth, can reach enormous values. Impulse currents NP, flowing through the earth circuits of the device, create noticeable voltage drops between different earth points, this can cause a failure.

In the signal circuit test NP pulses are injected through the "capacitive clamp", which in turn are laid all the wires that come to the device. The coupling capacity is small, a few picofarads, but for NP pulses, even relatively small capacitances are not a serious obstacle, their range is so wide. NP, which comes to the device from signal circuits, sooner or later gets to the device’s earth and then goes the same way as NP, injected into the ground circuit. Since, according to the standard, the amplitude of the signal NP is half the size of the ground signal, the signal signal path that hit the ground can no longer cause a worse effect than the ground signal light source. However, before the signal TM reaches the ground, it can cause a malfunction directly in the circuits associated with this signal.

The standard stipulates that the device under test should be on an insulating base at a distance of 100 mm from a solid grounded surface. This is an important requirement, because capacitive coupling is formed between the device and the earth, sometimes this alone is enough for failure.

Figure 1 conventionally shows some device consisting of nodes 1 ... 4. Nodes 1 and 2 are not connected to external circuits, but they can be lost due to "distortions" of internal ground caused by the passage of a current of interference Ignd (Fig. 1 shows the interference injected into the ground line). Nodes 3 and 4 are connected to external devices, therefore, in addition to failures due to the "skews" of the earth, they are additionally prone to failures due to disturbing currents I1 and I2 passing through their terminals.

The two types of checks specified by the standard (on the ground side and on the signal side) complement each other.

The tests stipulated by the standard, as well as Fig. 1, make it possible to single out three components of the noise immunity of the device to the NP, which are considered further in more detail:

Internal device ground
Barriers
Capacitive coupling

Internal device ground

As already mentioned, at the time of the passage of the NP on the internal earth of the device, a noticeable potential difference between different points of the earth is created ("imbalances"). For example, if nodes 1 and 2 (see Fig. 1) are digital nodes assembled on TTLSH logic, then a voltage difference of about 1 V between points "a" and "b" can cause a failure.

The main role in creating voltage drops is not the resistive, but the inductive component of the ground circuits. Due to the huge steepness of the leading fronts of the NP, even the meager inductances of earthen polygons or earthen layers in printed circuit boards are enough for failure.

Consider the equivalent circuit Fig.2.

The source of interference is the Vgen triangle pulse generator. The rise front interference 5 ns, the duration of the level of 50% is 50 ns (see voltage plot in Fig.2), the resistance of the source of interference Rgen is 50 Ohms, as specified by the standard. The amplitude of the interfering pulse of 1 kV, which corresponds to the relatively "soft" tests according to Table 1.

The capacitor Ccpl is the communication capacitance, and Lw is the inductance of the wires connected to the device. For the circuit in Fig. 1, the communication capacity of Ccpl consists of parallel-connected Cx1, Cx2 plus, possibly, capacities introduced by external devices.

The inductance Lw represents the total inductance of all conductors in the path of interference, with the exception of the inductance of the earth in the section under consideration (in our case, on section "a" - "b" Fig.1), which is designated as Lgnd. Suppose that the inductance of the earth Lgnd is 10 nG, and the inductance of the other circuits is 100 nG.

For orientation, the printed conductor 5 mm wide and 10 mm long has inductance more than 10 nG; a conductor 0.35 mm wide and 10 mm long is approximately 17 nG. A square polygon with dimensions of 25x25 mm has an inductance of more than 20 nG.

Figure 3 shows the voltage drop across Lgnd for the following cases:

C cpl = 10 pF, Lw = 100 nG
C cpl = 100 pF, Lw = 100 nG
With cpl = 0.1 μF, Lw = 100 nG
With cpl = 0.1 µF, Lw = 0

With the passage of interference on the inductance of the internal earth of the device creates a voltage drop sufficient for failure. It is very difficult to see such interference in the ground circuit using a storage oscilloscope for a number of reasons, including due to the limited sampling speed of most modern oscillographs.

From this it follows that even a continuous earthen layer will not save the device in Figure 1 from failures, and in it the “distortions” of the earth potentials during the passage of the NP can reach tens of volts.

The resistance of the device to the effects of non-volatile magnetic processes cannot be achieved only due to the thickening of earth conductors, the filling of free places of a printed circuit board by ground polygons or the use of multilayer boards. Due to the “thick” lands alone, it is possible to obtain a gain in noise immunity by about 1.5–3 times, which, against the background of the jamming signals in Figure 3, is completely inadequate.

The decoupling of external signals using optocouplers is also considered a good means of improving noise immunity, but in fact is not a reliable protection against NP. Typically, the optocoupler capacitance is equal to 0.5 pF, when substituting this value as Ccpl, the voltage drop across the inductance Lgnd in the circuit in Fig. 2 decreases to 4 V, which is still enough for a failure. If the device has several opto-decoupled I / O lines, then the capacitance Ccpl will be correspondingly larger.

Radical reduction of disturbing voltage in the device’s internal earth can be achieved by properly arranging the device and choosing the optimal grounding point. For example, it is quite obvious that in the inner earth of the device in Fig. 4, the interfering currents do not flow at all in the area “a” - “c”, respectively, nodes 1 and 2 have no reason for failure.

The device in Fig.4 can be represented as follows: the internal earth of the device is divided into two parts, clean ("a" - "c") and dirty (c - d). Noise currents do not flow along clean ground; all nodes that are potentially sensitive to interference can be connected to this ground (nodes 1 and 2). Interference currents flow only over muddy ground, with which you can only connect nodes that are not sensitive to interference (nodes 3 and 4).

The real picture is unlikely to be so idyllic as shown in Fig.4. The parasitic capacitance Cx very rarely manages to be concentrated only in muddy earth; in part it also exists in the clean left part. Due to this capacity, it is not possible to completely get rid of disturbing currents in a clean earth.

We illustrate this with a few examples.

Example 1

Figure 5 presents a diagram of the microcontroller's crystal oscillator. The basis of the generator is a high-speed inverting amplifier built into the microcontroller. DC mode is set by the built-in high-resistance resistor connected between the input and output of this amplifier. For the generator to work correctly, in addition to the external quartz resonator X1, two small capacitors, C1 and C2, are required. The capacitors and the microprocessor's earthen foot are connected to the internal earth of the device.

The connection points of the capacitors and the microcontroller to the PCB ground play a significant role. The slightest bias of ground potentials between C1 and VSS arising from the passage of the NP on the ground of the device will be amplified many times and will fall inside the microcontroller as a false short clock pulse. Since the duration of a false clock pulse is much less than the duration of the "real" clock pulses, the microprocessor's internal logic may come to an unpredictable state. The microprocessor will freeze, and not every built-in watchdog timer will be able to reset it, since in some microcontrollers, watchdog timers are clocked from a common generator, and they themselves can “hang” after such interference.

Figure 6 shows examples of the layout of this node on the printed circuit board.

The fragment on the left is diluted in the usual way, on the assumption that the potentials of the earths are equal at all points of the printed circuit board. Capacitors C1 and C2 are connected to the ground in the same way as all the other circuit elements, the thickness of the ground conductors is large. Such wiring is common, but, unfortunately, it does not provide good noise immunity.

The fragment on the right is diluted so that the interfering current does not flow along the path connecting the capacitors C1 and C2 with the microcontroller's earthen leg. This path forms a piece of clean land. The noise immunity of the device with such a wiring is maximum.

Example 2

The microcontroller reset input is another circuit affected by nanosecond interference. Often, developers ignore this obvious fact and use an extensive reset circuit directly connected to various nodes on the board. Land skews between the source of the reset signal (often a power supervisor) and the microcontroller cause a false reset of the device.

It is easy to solve this problem schematically, it is enough to add a simple RC-chain to the input of the microcontroller, as shown in Fig.7. However, such a decision must be accompanied by proper land distribution, otherwise it will not bring any benefit.

The wiring requirements for the track connecting C3 to the microcontroller's earthen foot are the same as for the first example: no other parts except C3 can be connected to this track. The only exceptions are quartz piping capacitors (C1 and C2 in Figure 5).

Example 3

Provide high noise immunity of the device at the stage of the overall layout. A typical device, the layout of which did not take into account noise immunity issues, is shown in Fig. 8. To connect external signals and power it uses all four edges of the printed circuit board. The microprocessor is located almost in the center of the printed circuit board, that is, in a place most susceptible to the influence of nanosecond interference. In the case of using solid earth, it is very likely that such a device will fail.

Without changing the layout, a significant improvement in noise immunity in such a device can be achieved if the land is divided into clean and dirty, as conventionally shown in Fig. 8. The outer contour of the earth is a dirty earth, it is specifically designed to spread nanosecond interference. Noise sensitive devices should not be connected to the dirty ground.

The inner "peninsula" of pure land is connected to dirty land at one point. In all the signal lines passing between clean and dirty earth, you must add resistors or chokes to block the path of interference (barriers).

A further improvement in noise immunity is achieved by rearranging the device, as shown in Figure 9. It can be seen that all terminals are concentrated on one dirty side of the board. Thus, the path of propagation of interference on the ground board is significantly reduced.

Barriers

After the internal land devices are divided into clean and dirty, the question arises - how to prevent interference from the dirty land in the clean? For example, in the device in Fig. 4, node 2 is connected to clean ground, but it exchanges signals with node 3, which is subject to interference. In example 3 above, it was mentioned that the signal circuits connecting the nodes on clean and dirty earth should contain noise barriers - resistors or chokes. Practice shows that the widespread use of barriers usually increases the noise immunity of the device several times.

Example 4

Consider a microcontroller that controls a powerful load with a relay. A bipolar transistor is used to control the relay.

Relay contacts are a source of nanosecond interference. In addition, external interference quite easily pass through the relay due to its parasitic pass-through capacitance and mounting capacities. However, neither the relay nor the transistor Q1, by themselves, are influenced by the NP.

The ground pin of the VSS microcontroller is connected to the clean ground, the emitter of the Q1 transistor is dirty. Resistor R1, in addition to its main function, serves as a barrier to the spread of interference from the dirty part to the clean. The throughput capacitance of the resistor is usually small, on the order of 0.2 ... 0.3 pF, therefore the resistors create an effective barrier for NP. In severe cases, to reduce the passage capacity, you can include two or three resistors in series.

If a field-effect transistor were used instead of a bipolar one, then R1 would have to be put just as a barrier, although it would not be necessary for the circuit to function.

Example 5

Another typical example is the connection of optocouplers to a microcontroller. Figure 11 shows a fragment of the input and output optocoupler.

The emitter of the input optocoupler U1 is connected to the dirty ground, since due to the 0.5 pF pass-through capacitance, the optocoupler is translucent for NP. The low-speed optocoupler itself is quite indifferent to NPs, but it should be noted that optocouplers with a connected phototransistor base output sometimes “catch interference”, therefore it is preferable to use optocouplers without outputting the base.

Resistor R1 can be connected to both dirty and clean power, since the resistor itself is a barrier that prevents the passage of a non-energizer to a clean power supply.

Resistor R2 with a magnitude of 1k ... 100k serves as a noise barrier between the optocoupler and the microcontroller. Capacitor C1 is not a required element, however, the presence of this capacitor further improves noise immunity, as it reduces the disturbing current flowing through the microcontroller’s earthen leg. C1 and microcontroller connected to clean ground.

The anode of the LED output optocoupler U2 is connected to a dirty power supply + 5V. The current-setting resistor R3 simultaneously serves as an interfering barrier. In a particularly difficult interference environment, it is useful to bridge the LED of the optocoupler with a capacitor of 1 ... 10 nF, or at least a resistor.

In the case when it is impossible or inconvenient to connect an optocoupler to a dirty power supply, you can divide the current-setting resistor by two, as shown for the U3 optocoupler. Resistor R5 serves as a noise barrier between the optocoupler and the clean + 5V power bus.

Capacitive coupling

Part of the disturbing current in Figure 1 flows through the coupling capacitance Cx. Recall that when a device is tested for noise immunity, it must be placed on an insulating base 100 mm above a solid ground. Sometimes only a ground connection capacity is sufficient for a device failure.

The division of land into clean and dirty by itself does not reduce the total value of capacitive coupling. The ratio of communication capacities for clean and dirty land corresponds to the ratio of their areas.

Quite obvious methods of dealing with capacitive coupling are land redistribution, reduction of conductor areas and partial shielding.

Note the position of the microcontroller in Figure 9. It is located in the corner of the board, so due to the capacitive coupling a relatively small current will flow through it. In Figure 8, the microcontroller is located differently. A large polygon of pure land to the right of it has a significant capacitive connection with the true earth, so the probability of failure will be much greater.

Example 6

Figure 12 shows two options for the layout of the earth ground under the microcontroller. Instead of quartz and capacitors, a three-output ceramic resonator is used for mounting on the X1 surface. The wiring is made for a hypothetical "correct" microcontroller, the developers of which took care of noise immunity and positioned the earth output between the generator terminals. This is not utopia, the Renesas M16C family of microcontrollers, which are among the most noise-tolerant 16-bit microcontrollers, really have a similar pin layout.

Unused pins of the microcontroller are connected to the internal earth ground.

In Fig.12, on the left, the ground is connected to the clean earth of the board with several vias. Due to this, the device is not noise-resistant. Interference current flowing through the clean earth and leaving the true earth through a capacitive coupling creates a potential gradient ("skew"). The vias pass the bias to the ground of the microcontroller. Interference current flows partially through the legs of the microcontroller connected to the test site, which can cause a malfunction.

In Fig.12, on the right, the microcontroller’s earthen ground is connected to pure ground at one point, next to the microcontroller’s earthen foot. The noise immunity of the device is maximum, because the clean earth on the opposite side of the board becomes a kind of screen protecting the “super-clean” land of the landfill.

Crosstalk

In addition to external sources of nanosecond interference, various nodes inside the device themselves can generate mutual interference.

Modern digital chips, especially LSI, are also sources of NP. At the time of switching, hundreds and thousands of transistors inside the LSI change their states, as a result, hundreds and thousands of parasitic capacitors are recharged (for example, the capacitances of the gates in CMOS chips). As a result, pulsed currents of nanosecond and sub-nanosecond duration and large amplitude flow through the legs of the earth and the power supply of the microcircuits. Spreading over the tires of the earth and the power supply of the board, these currents somewhat impair the overall noise immunity of the device, but they themselves, as a rule, are not the cause of failures.

To reduce the harmful effects of these currents, ceramic decoupling capacitors are placed in the power supply circuit next to the microcircuits. Capacitors should be as close as possible to the feet of the ground and power to reduce the size of the circuit through which recharge currents circulate.

This is a truism. However, quite often we hear such statements: "my device failed, I put more capacitors in the power supply, but it still fails." It seems that some developers believe that decoupling capacitors are placed to protect against external interference. This, of course, is a fallacy. As a consequence of such a delusion, there are sometimes motherboards where decoupling capacitors are located far from the microcircuits, although nothing prevented them from putting them much closer to the power pins.

The power supply supervisor chip deserves special consideration. As you know, it works infrequently, so that NP almost does not create interference. However, she herself is subject to the influence of nanosecond interference, so it is necessary to install a ceramic decoupling capacitor near the power supervisor. This is a rare case when such a capacitor is in fact a filter for external interference.

Design of anti-interference devices